SC402B
28
Applications Information (continued)
PCB Layout Guidelines
The optimum layout for the SC402B is shown in Figure 17.
This layout shows an integrated FET buck regulator with a
maximum current of 10A. The total PCB area is approxi-
mately 25 x 29 mm with single side components.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
C
SS
BST, ILIM, and LX
C
IN
and C
OUT
placement and Current Loops
"
"
"
"
"
"
"
IC Decoupling Capacitors
A 1 糉 capacitor must be located as close as pos-
sible to the IC and directly connected to pins 3
(VDD) and 4 (AGND).
Another 1 糉 capacitor must be located as close
as possible to the IC and directly connected to
pins 3 (VDD) and PGND plane.
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
"
"
"
"
"
VOUT Plane on top
and bottom layer
L
C
IN
RFB2
RFB1
LX plane on top and
bottom layer
All components shown Top Side
AGND plane on
inner layer
V
IN
plane on
top and/or
bottom layer
RGND AGND connects to
PGND close to IC
Pin 1 marking
IC with vias for
LX, AGND, VIN
C
OUT
PGND on inner
or bottom layer
Vout sense trace
on inner layer
VDD Decoupling Capacitor
Cer.
C
IN
SP or
POSCAP
CTOP
PGND on top
layer
Figure 17 PCB Layout
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